The present invention relates to a structure of a semiconductor device in which a gate electrode is provided within a trench.
For switching operation at a large current, power MOSFETs or IGBTs are used, and in order to provide a large operating current, an element of trench gate type in which a gate electrode is provided within a trench is particularly preferably used. In addition, conventionally, as the material for a semiconductor substrate constituting such element, Si has been in a widespread use, but in recent years, silicon carbide (SiC), which has a band gap larger than Si and can constitute an MOSFET in the same manner as Si, has been used. In this case, as compared to the case where Si is used, operation at a high voltage and a large current, is allowed, however, the gate oxide film within the trench becomes easy to be broken down with a high voltage, and therefore, a structure that can raise the breakdown voltage has been used.
The structure of a power MOSFET of trench gate type that uses SiC is disclosed in, for example, Patent Documents 1 and 2. FIG. 6 is a sectional view showing a structure of such semiconductor device (a power MOSFET) 200. Here, with a semiconductor substrate 50, which is formed of SiC, a plurality of trenches T (three are shown within the range of the figure) are formed in parallel in a direction perpendicular to the paper sheet surface. Within the semiconductor substrate 50, an n+ layer (a drain layer) 11 of n type (a first conductivity type), in which a donor has been doped at a high concentration; an n− layer (a drift layer: a first semiconductor region) 12, in which a donor has been doped at a low concentration; a p layer (a body layer: a second semiconductor layer region) 13 of p type (a second conductivity type) are formed sequentially from the bottom side. As a surface layer of the semiconductor substrate 50 that is on the p layer 13, an n+ layer (a source region: a third semiconductor region) 14 is formed. The trench T is formed from the surface of the semiconductor substrate 50 such that it reaches the n− layer 12 from the n+ layer 14, and within the trench T, a gate electrode (a control electrode) 22 is formed through a gate oxide film 21. In addition, in the surface of the semiconductor substrate 50, a p+ layer 15, in which an acceptor has been doped at a high concentration is locally formed, and this p+ layer 15 is connected to the p layer 13 thereunder.
On the surface side of the semiconductor substrate 50 (on the top side in FIG. 6), a source electrode 23 is formed so as to be in contact with the n+ layer 14 and the p+ layer 15. Here, on the top side of the trench T, the gate electrode 22 is insulated from the source electrode 23 by a interlayer insulating layer 25. In addition, on the rear surface side of the semiconductor layer 50 (the bottom side in FIG. 6), a drain electrode 24 is formed so as to be in contact with the entire face of the n+ layer 11. With this structure, at the time of operation, the n+ layer 14 and the p layer 13 are provided with a potential of the source electrode 23 (a source potential: generally a ground potential), while the n+ layer 11 is provided with a potential of the drain electrode 24 (a drain potential: generally a positive high potential). To the gate electrode 22, a potential that is close to the source potential and is according to the on-off control is applied. In on state, in the p layer 13 opposed to the gate electrode (in the p layer 13 at a side face of the trench T), a channel is induced, and therefore, across the source electrode 23 and the drain electrode 24, a current flows along a side wall of the trench T within the p layer 13, and in a vertical direction within the n− layer 12. On the other hand, in off state, a depletion region spreads from the circumference of the trench T and the interface (the pn junction) between the p layer 13 and the n− layer 12 towards the n− layer 12. The electric field in off state is applied to the gate oxide film 21 and to within such depletion region, and thus by expanding the depletion region appropriately, the intensity of such electric field is reduced, whereby the breakdown voltage can be enhanced. Thus, the donor concentration within the n− layer 12 is set at a low value.
However, with this structure, even in the case where the depletion region on the side of the n− layer 12 has been expanded, in off state, the intensity of the electric field especially within the gate oxide film 21 in the bottom end part of the trench T tends to be increased, thereby the breakdown voltage for such semiconductor device 200 being limited in some cases. Here, in the structure in FIG. 6, in a place separate from the trench T on the lateral side of the trench T, an electric field relaxation p-layer (a fourth semiconductor region) 16 is locally provided more deeply than the trench T, being connected to the p layer 13 on the upper side thereof. In off state, also around this electric field relaxation p-layer 16, a depletion region is formed. Particularly, since the electric field relaxation p-layer 16 is formed deeper than the trench T, the depletion region on the side of the electric field relaxation p-layer 16 is formed to a greater depth on the lateral side of the trench T. The depletion region on the side of the bottom part of the trench T is connected to such deeper depletion region on the side of the electric field relaxation p-layer 16, and therefore in the portion where a connection is produced, the breadth of the depletion region is increased, whereby the intensity of the electric field that is applied to the gate oxide film 21 in the bottom end part of the trench T can be decreased. In this way, by forming the electric field relaxation p-layer 16 locally deeply, the intensity of the electric field that is applied to the gate oxide film 21 in the bottom end part of the trench T in off state can be decreased, whereby the breakdown voltage for this semiconductor device 200 can be improved.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-117593
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2013-69940
In the above-described structure, in on state, the current flows along the side wall of the trench T within the p layer 13, and therefore, within the n− layer 12, most of the current will not flow in the region just under the trench T, and will flow in a vertical direction in the region other than that just under the trench T (i.e., the region around the trench T). Here, as described above, in the region where the trench T is not formed when viewed from the top face, the electric field relaxation p-layer 16 exists, and therefore, the path for a current along a vertical direction in the n− layer 12 is narrowed down by the electric field relaxation p-layer 16, thereby it having been difficult to decrease the resistance to the current within the n− layer 12. Thereby, the current that can be caused to flow in on state (the on-current) has been limited.
Consequently, a semiconductor device of trench gate type that has achieved both large on-current and high breakdown voltage in off state has been demanded.
The present invention has been made in view of such problems, and is intended to provide a semiconductor device with which the above-mentioned problems can be solved.